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Mid-Term System Architecture & Base Conversion Lab

SS1 Term 1 • Week 6
About 45 minutes
Learning goals: Synthesize system architecture, bus communication, and CPU register operation. • Demonstrate fluency across Decimal, Binary, Hexadecimal, and Octal conversions. • Execute signed binary arithmetic and two's complement subtraction without arithmetic errors. • Diagnose hardware bottlenecks comparing bus width, clock frequency, and memory capacity.

Congratulations on reaching the mid-term of SS 1! Over the past five weeks, you have mastered the theoretical foundations of computer engineering: - The Von Neumann Architecture and Tri-Bus System in Week 1, - Binary and Decimal Conversions in Week 2, - Hexadecimal and Octal Shorthand in Week 3, - Two's Complement Signed Arithmetic in Week 4, - And the Internal Specialized CPU Registers (PC, MAR, MDR, CIR, ACC) in Week 5.

Today, you step into the role of a Lead Computer Hardware & Systems Engineer. You will synthesize number theory with hardware architecture, solve rigorous conversion drills, and analyze system performance bottlenecks.

Learning Outcomes

By the end of this review lab, you will be able to:

  1. Perform multi-base conversions rapidly between Base 10, Base 2, and Base 16.
  2. Execute signed two's complement operations and verify against decimal calculations.
  3. Trace instruction execution using precise Register Transfer Notation (RTN).
  4. Calculate memory addressability and bus throughput.

Comprehensive Review Summary Matrix

=========================================================================
SYSTEM COMPONENT         FUNCTION                         BUS CONNECTED
=========================================================================
Program Counter (PC)     Holds address of next inst.      Internal CPU Bus
Memory Address Reg (MAR) Holds memory address targeted    Address Bus (Unidir)
Memory Data Reg (MDR)    Holds fetched/written data byte  Data Bus (Bidir)
Current Inst Reg (CIR)   Holds opcode & operand for CU    Internal CPU Bus
Accumulator (ACC)        Holds ALU intermediate results   ALU Data Path
=========================================================================

The Systems Engineering Problem Set

Solve these multi-part engineering problems in your notebook:

Problem 1: Multi-Base Conversion Circuit

A network sensor node transmits a status telemetry code: $(10111101)2$. 1. Convert this binary byte to Hexadecimal:
- Nibble 1 (left): $1011_2 = 11} = \mathbf{B{16}$
- Nibble 2 (right): $1101_2 = 13$} = \mathbf{D}_{16
- Hex Code: 0xBD 2. Convert this binary byte to an unsigned Decimal integer:

$$128 + 0 + 32 + 16 + 8 + 4 + 0 + 1 = \mathbf{189_{10}}$$

  1. If this byte is interpreted as an 8-bit signed Two's Complement integer, what is its negative decimal value?
  2. Since MSB = 1, it is negative.
  3. Value $= -128 + (189 - 128) = -128 + 61 = \mathbf{-67_{10}}$.
    (Verification: Invert $10111101 \to 01000010 + 1 = 01000011_2 = 67_{10} \implies -67_{10})$.

Problem 2: Bus Bandwidth Calculation

A graphics workstation has a 64-bit wide Data Bus operating at a bus clock frequency of 3.2 GHz ($3.2 \times 10^9\text{ cycles/second}$). 1. How many bytes can the bus transfer per clock cycle?

$$\text{Bytes per cycle} = \frac{64\text{ bits}}{8\text{ bits/byte}} = \mathbf{8\text{ bytes}}$$

  1. Calculate the maximum theoretical data throughput in Gigabytes per second (GB/s):

$$\text{Bandwidth} = 8\text{ bytes} \times 3.2 \times 10^9\text{ cycles/sec} = \mathbf{25.6\text{ Gigabytes/second}}$$

Practical Class Activity: The Register Simulation Challenge

Write out the four-step Register Transfer Notation (RTN) for fetching an instruction from memory into the CPU, and explain what happens to the Program Counter during step 2.

Step 1: MAR <- [PC]
Step 2: PC  <- [PC] + 1
Step 3: MDR <- [Memory]_MAR
Step 4: CIR <- [MDR]

Explanation of Step 2: The Program Counter increments immediately after its address is sent to the MAR so that the processor is already prepared for the next sequential instruction while memory is retrieving the current one!

Common Mistakes & Corrections

Common Mistake Why It Is Incorrect Proper Correction
"Confusing unsigned binary value with two's complement value." Unsigned treats all bits as positive weights; signed uses the MSB as $-2^{N-1}$. Check whether the context specifies signed or unsigned before calculating.
"Assuming 64-bit data bus means 64 bytes." 64 bits equals 8 bytes ($64 / 8 = 8$). Always divide bits by 8 to determine byte capacity.

Notebook Summary

Mid-Term Golden Takeaway

  • Base conversions form the language of hardware: Binary is the physical circuit state; Hexadecimal is human-readable shorthand ($1\text{ hex digit} = 4\text{ bits}$).
  • Two's complement enables microprocessors to subtract using addition hardware alone ($A - B = A + (-B)$).
  • Registers (PC, MAR, MDR, CIR, ACC) coordinate the fetch-decode-execute cycle with microsecond precision.

Check your understanding

What is the two's complement 8-bit representation of -1?
If a processor has a 32-bit data bus and operates at a clock speed of 2.0 GHz, how many bytes of data can theoretically travel across the bus per second?
Which register transfer step correctly increments the Program Counter to point to the next instruction?
What is the hexadecimal representation of the binary number (1111 1010 1100 0101)₂?
Feedback appears after you check your answer.